1. Field of the Invention
The invention relates to a phase-locked loop system, and more particularly to a sigma-delta modulated discrete time oscillator.
2. Description of the Related Art
A typical video system uses frame sync (Vsync) or line sync (Hsync) signal for video timing. To digitize video analog signal, a clock recovery system is needed to regenerate an original pixel clock from Hsync signal or Vsync signal. The Hsync signal for video timing is taken for example to illustrate a typical analog PLL (phase-locked loop) system.
FIG. 1 is a block diagram illustrating a typical analog PLL system. The analog PLL system 100 comprises a phase detector 102, a charge-pump circuit 104, a low pass filter 106, a voltage-controlled oscillator 108 and a divider 110. The phase lock loop system 100 receives a Hsync signal SI for video timing. The frequency of the Hsync signal is around 15 kHz.
There is no Hsync signal for several lines in a video system for each frame. A typical analog PLL system needs to maintain an input clock of a voltage-controlled oscillator for several lines. The analog PLL system 100 uses the low pass filter 106 to maintain this input clock.
The low pass filter 106 is coupled to an output terminal of the charge-pump circuit 104. The output of the low pass filter 106 drives the voltage-controlled oscillator 108 to generate a required pixel clock S0. The required pixel clock S0 is fed back to the phase frequency detector 102 through the divider 110. The phase detector 102 receives the required pixel clock S0 and the Hsync signal SI to generate a phase error output to the charge-pump circuit 104.
Because the frequency of the Hsync signal SI is around 15 KHz, the pole of the low pass filter 106 is kHz. Thus, values of components forming the low pass filter 106 such as capacitor or resistor are high. These components form an extra loop filter. The ground of the extra loop filter is physically different from analog ground of the voltage-controlled oscillator 108. Different ground noises generate jitter, with the most serious problem being long term jitter. Because the divisor of the divider 110 is too large, such as 1888 or 1716, the accumulated jitter will influence the detected result of the phase detector 102 after a period of the divisor.
To overcome this drawback, a digital PLL approach has been provided. FIG. 2 is a block diagram illustrating a typical digital PLL system. The digital PLL system 200 comprises a phase detector 202, a linear gain circuit 204, a digital low pass filter 206, a discrete time oscillator 208 and a clock divider 210. Using a high frequency fixed clock Sc, such as 135 MHz, generated by another analog PLL system with a smaller low pass filter, the analog clock recovery system can be replaced with digital implementation. Analog phase errors output from the phase detector 102 represented by xcex94t are replaced with digitized counter differences output from the phase detector 202. The charge-pump circuit 104 is replaced with the linear gain circuit 204. The analog low pass filter 106 for filtering high frequency unwanted signal is replaced by the digital low pass filter 206. Output of the digital low pass filter 206 and the control signal Sc controls the discrete time oscillator 208 to generate a required pixel clock So.
The digital PLL approach can solve the problem of long term jitter. However, the traditional digital PLL approach suffers from inaccurate control values for the discrete time oscillator 208.
Therefore, what is needed is a way to accurately control a discrete time oscillator in a digital PLL system, unencumbered by the long term jitter.
It is an object of the present invention to provide a discrete time oscillator accurately controlled by a sigma-delta modulator in a digital PLL system.
It is another object of the present invention to provide a sigma-delta modulated discrete time oscillator used in a digital PLL system unencumbered by long term jitter.
The present invention thus provides a sigma-delta modulated discrete time oscillator. The sigma-delta modulated discrete time oscillator comprises a synchronous counter and a sigma-delta modulator. The sigma-delta modulator operating in a first clock receives a control signal to generate a divider pattern output. The control signal provides a DC value for the frequency of the first clock. The divider pattern comprises a plurality of numbers, values of which are synchronous with the rate of the first clock. The synchronous counter operates in a second clock. In the synchronous counter, the second clock is divided by the divider pattern to generate the first clock. The frequency of the second clock is much higher than the frequency of the first clock.
In another aspect of the invention, a phase-locked loop system is disclosed. The phase-locked loop system, comprises a phase detector, a digital low pass filter, a sigma-delta modulated discrete time oscillator and a clock divider. The phase detector receives a referenced clock and a feedback clock to find a phase error output. The digital low pass filter is coupled to the phase detector, for receiving the phase error to generate a control signal. The control signal provides a DC value for a frequency of a first clock. The sigma-delta modulated discrete time oscillator comprises a synchronous counter and a sigma-delta modulator. The sigma-delta modulator operating in a first clock receives the control signal to generate a divider pattern output. The divider pattern comprises a plurality of numbers, values of which are synchronous with the rate of the first clock. The synchronous counter operates in a second clock. In the synchronous counter, the second clock is divided by the divider pattern to generate the first clock. The frequency of the second clock is much higher than the frequency of the first clock. The clock divider receives the first clock and generates the feedback clock feedback to the phase detector.